COMPUTER ARCHITECTURE
Academic Year 2022/2023 - Teacher: DAVIDE PLATANIAExpected Learning Outcomes
Knowledge and understanding
- The student will know:
- the basic techniques for the design of combinational and sequential digital circuits.
- the elementary modules that make up a processing system
- the main architectures of the instruction set.
- the basic architectures of RISC processors
- the assembly of an educational processor
- microcontrollers and related development environments
Applied knowledge and understanding
The student will be able to:
- design simple combinational and synchronous sequential circuits
- evaluate the performance of a computer
- write programs in the assembly language of a compatible Intel x386 processor
- use the development environment of a microcontroller
Autonomy of judgment
The student will be able to evaluate the impact of architectural choices on the performance of computers.
Communication skills
The student will be able to explain in a clear and rigorous way the acquired knowledge and the ways in which to apply these for the design of simple processing systems.
Ability to learn
The student will be able to independently learn:
- additional basic characteristics of the processor architectures
- the assembly of other processors
Course Structure
Required Prerequisites
Attendance of Lessons
Detailed Course Content
Part I - Design of digital systems
1.1 Design of combinatorial networks
Switching algebra. Minimum Boolean expressions. Minimization using the Karnaugh and Quine-McCluckey maps method.
1.2 Design of synchronous sequential networks
Introduction to sequential machines. The memory elements: the bistables. Synthesis of synchronous sequential networks. Minimization of finite state machines.
Part II - Computer architecture
2.1 The computer: abstraction and technologies
The types of calculators and their characteristics. The components of an electronic computer and their organization. Evaluation of the performance of a computer. Amdhal's law.
2.2 The computer language: Assembly
Instruction Set of processors. Instruction Set Architecture Intel x386. Creating and running executable Assembler, linker and loader. Configuration of the development environment for Linux. X386 instructions, Subroutine calls and System Call. Access to memory. Array. Strings. Stack Management.
2.3 Computer organization
Sequential organization of a processor. Datapath of a sequential processor. Control unit of a sequential processor. Pipeline organization of a processor.
2.4 The memory subsystem.
Static and dynamic RAM memories. Asynchronous and synchronous memories. Memory organization. Cache memories. Block placement, block identification, block replacement and writing policies. Memory performance evaluation. Techniques for improving cache performance.
2.5. The Input / Output subsystem:
Polling. Interrupts. Interrupt vector. Interrupt priority management. Direct Memory Access (DMA).
2.6 Microcontrollers
Microprocessors vs Microcontrollers (MCU). General characteristics of an MCU. Block diagram and on-chip integrated peripherals. Embedded Core. Memory. General Purpose IO (GPIO). Timers and Counters. Serial communication interfaces and peripherals. Development environment for microcontrollers - writing simple programs for managing GPIOs and peripherals.
Textbook Information
[T1] Fummi, Sami, Silvano, “Progettazione digitale”, 2/ed McGraw-Hill
[T2] Patterson, Hennessy, “Computer organization and design”
[T3] Bucci, “Architettura e organizzazione dei calcolatori elettronici: fondamenti”, McGraw-Hill
[T4] Online learning resources provided by teacher
Course Planning
Subjects | Text References | |
---|---|---|
1 | Design of combinatorial networks. Switching algebra. Minimal Boolean expressions. Minimization by the method of Karnaugh and Quine-McCluckey maps. | T1 chapter 3 and 4, T4 |
2 | Design of synchronous sequential networks. Introduction to sequential machines. The elements of memory: the bistables. Synthesis of synchronous sequential networks. Minimization of finite state machines. | T1 chapter 5 and 6, T4 |
3 | Components of a digital system. Multiplexer, Decoder, Encoder, Comparator, Registers, Register file. | T1 chapter 7 and 8, T2 chapter 3, T4 |
4 | Carry Over propagation adder Carry-over advance adde.Multiplier and divider. Design of an ALU | T1 chapter 7 an 8, Y2 chapter 3, T4 |
5 | The types of calculators and their characteristics. The components of a computer. Organization of electronic computers. | T2 chapter 1, T3 chapter 5, T4 |
6 | Microprocessors Instruction Set Architerctures | T2 chapter 2, T3 chapter 5, T4 |
7 | Sequential organization of a processor. Datapath of a sequential processor. Control Unit of a sequential processor: wired and microprogrammed design. | T2 chapter 4, T3 chapter 7, T4 |
8 | Pipeline processor | T2 chapter 4, T4 |
9 | Instruction Set Architecture Intel x386. General registers, pointer registers, segment registers, and flags. The 32-bit memory model. CPU RAM interaction. Compatibility with 64-bit Intel processors. | T4 |
10 | ASM programming: Assembler, Linker and Loader. Configuration of the development environment for Linux. Schema of an x386 Assembler program in a Linux environment. | T4 |
11 | Arithmetic and logical instructions. Addressing instructions. Flow control: conditional and unconditional jumps. LODS, STOS, MOVS – exercises. Linux services – int 80h. Files in Linux (STDIN, STDOUT and STDERR). Exercises | T4 |
12 | The Stack: PUSH-POP, CALL-RET, INT-IRET. Command-line applications and parameter passing. From C to Assembly with gcc and nasm. Passing parameters through the stack. Application examples. | T4 |
13 | The Memory Subsystem. Classification of memories. Static Ram and Dynamic RAM. Read and write cycles. Asynchronous and synchronous DRAM. Organization of memory. Address decoding. | T2 chapter 5, T3 chapter 8, T4 |
14 | Cache memories. Evaluation of cache memory performance. Block placement, block identification, block replacement and writing policies. | T2 chapter 5, T3 chapter 8, T4 |
15 | Techniques for improving cache performance. | T2 chapter 5, T3 chapter 8, T4 |
16 | The Input/Output subsystem: Polling. Breaks. Vectorized breaks. Priority management. Direct access to memory. | T3 chapter 13, T4 |
17 | Structure of an MCU: A computer in a single chip. General characteristics. Typical applications. Core. Memory. GPIO. Serial communication devices. Comparisons with microprocessors. MCU Market. | T4 |
18 | MCU applications. Exercises with Arduino or STM32 | T4 |
Learning Assessment
Learning Assessment Procedures
The exam consists of a single written and computer test.
First part (11 points)
- three questions on logical networks;
Second part (21 points)
- a question about assembly programming;
- a question about calculating the performance of computers;
- a question on computer architectures;
- a question about microcontrollers
To pass the test it is necessary to obtain a minimum score of 18, with at least 6/11 points for the questions on logic networks and at least 12/21 points for the rest of the task.
Distance learning could be used if COVID emergency requires it