Maurizio PALESI
Maurizio Palesi is a Full Professor of Computer Architecture at the University of Catania and a Visiting Associate Professor at the Indian Institute of Technology Guwahati. His research focuses on computer architectures, including many-core systems, Network-on-Chip, hardware accelerators, approximate computing, and quantum architectures. He has authored more than 200 scientific publications in international journals and conferences.
Academic Profile
Maurizio Palesi is a Full Professor of Computer Architecture (IINF-05/A) at the Department of Electrical, Electronic and Computer Engineering, University of Catania. He is also a Visiting Associate Professor at the Indian Institute of Technology Guwahati.
His research activity focuses on computer architectures, with particular emphasis on many-core systems, Network-on-Chip, domain-specific hardware accelerators, approximate computing techniques, and, more recently, multi-chip quantum architectures.
Education and Career
He received his PhD in Computer Engineering and Telecommunications from the University of Catania, where he also graduated with honors in Computer Engineering. Following research experiences and visiting periods abroad (including the University of California, Riverside and Jönköping University), he held academic positions at Kore University of Enna and later at the University of Catania, where he served as Associate Professor and subsequently Full Professor.
Teaching Activities
He is actively involved in teaching at both undergraduate and graduate levels in Computer and Electronic Engineering programs, delivering courses such as Fundamentals of Computer Science, Computer Architecture, and IoT-based systems. He has also delivered seminars and courses abroad and supervised numerous undergraduate and PhD theses.
Research Activities and Projects
He serves as scientific coordinator and principal investigator in several national and European research projects, including PRIN and Horizon Europe initiatives, as well as projects in High Performance Computing, IoT, and quantum systems. He collaborates with public institutions and industry partners and is involved in large-scale research initiatives in HPC and emerging computing systems.
Editorial and Scientific Activities
He is Associate Editor of several leading international journals, including IEEE Transactions on Computers and ACM Transactions on Design Automation of Electronic Systems, and has served as Guest Editor for numerous special issues.
He is actively engaged in the international research community, having served as chair and member of organizing and technical committees of major international conferences, and as founder of the NoCArc workshop.
Scientific Production
He is author of more than 200 scientific publications in international journals and conferences, with over 5,000 citations and an h-index of 36 (Google Scholar). His research output focuses on advanced computing architectures, embedded systems, and emerging technologies.
Awards and Recognitions
He has received several international recognitions, including Best Paper Awards and awards for his reviewing activity. He is an IEEE Senior Member and an ACM member.