COMPUTER ARCHITECTURES, MICROCONTROLLERS AND IoT TECHNOLOGIES M - ZModule COMPUTER ARCHITECTURES
Academic Year 2025/2026 - Teacher: Giuseppe ASCIAExpected Learning Outcomes
The course presents the fundamental concepts of computer architectures.
In the first part the course introduces the techniques and methodologies for the design of digital systems.
In the second part, the course presents the components of a computer and their organization, some instruction set architectures of the processors, some techniques for an efficient implementation of the processors and the memory subsystem.
Furthermore, in order to better understand the functioning of the processor, the course introduces the student to the assembly programming of a RISC processor.
Knowledge and understanding
The student will know:
- the basic techniques for the design of combinational and sequential digital circuits.
- the elementary modules of a computer
- the main instruction set architectures.
- the basic architectures of RISC processors
- the assembly of a RISC processor
Applying knowledge and understanding
The student will be able to:
-design simple combinational and synchronous sequential circuits
- evaluate the performance of a computer and the impact of architectural choices on performance
-write programs in the assembly language of a RISC processor
Making judgements
The student will be able to assess the impact of architectural choices on the performance of a computer.
Communication skills
The student will be able to clearly and rigorously present the acquired knowledge and how to apply it for the design and evaluation of simple computing systems.
Learning skills
The student will be able to independently learn:
- additional basic features of processor architectures
- the assembly of other processors
Course Structure
The course will be organized in lectures, exercises, practical experiences and presentation of use cases.
If the teaching is given in a mixed or remote mode, the necessary changes with respect to what was previously stated may be introduced, in order to respect the program planned and reported in the syllabus.
Required Prerequisites
Attendance of Lessons
Attendance is not required, although strongly recommended.
Detailed Course Content
Part I Digital Design
*1.1 Combinational circuits design
Switching Algebra. Minimum Boolean expressions. Minimization using Karnaugh maps and Quine-McCluckey method.
*1.2 Synchronous sequential circuits Design
Introduction to sequential machines. The memory elements. Synthesis of synchronous sequential circuits. Minimization of finite state machines.
1.3 Design of a digital system
Design flow of a digital system. Datapath and control unit. Components of a digital system. Arithmetic circuits.
Part II Computer architecture
*2.1 Computer abstractions and technology
The types of computers and their characteristics. The components of a computer. Computer Organization. Computer performance evaluation. Amdhal’s law.
*2.2 The computer language: the Assembly
Instruction Set Architecture. Translation and starting a program: assembler, linker, and loader. RISC-V Instruction Set Architecture. An Instruction Set Simulator for RISC-V processor. Assembly of RISC-V processor. Arithmetic/logical instructions. Memory access. System calls. Array. String. Procedure calls
*2.3 Computer Organization
Sequential organization of a processor. Datapath of a sequential processor. Control unit of a sequential processor.
Organization of pipelined processor. Pipeline Hazard. Performance evaluation of a pipelined processor. Techniques for detecting and resolving pipeline hazards. Code scheduling for hazard minimization.
2.4 The Memory subsystem.
Static and dynamic RAM memories.
*Cache memories. Block placement policies, block identification, block replacement and write policy. Memory Performance. Techniques for improving cache performance.
Textbook Information
[T2] Patterson, Hennessy, “Struttura e progetto dei calcolatori – Progettare con RISC-V”, Zanichelli
[T3] On line Course material ( Microsoft Teams Computer Architectures (M-Z), AA. 25-26 code: axe7wtv)
Course Planning
| Subjects | Text References | |
|---|---|---|
| 1 | Combinational circuits design. Algebra. Minimum Boolean expressions. Minimization using Karnaugh maps. Estimated time: Estimated time: 4 hours lectures + 4 hours exercises | T1 chapters 3 and 4, T3 |
| 2 | Synchronous sequential circuits design. Introduction to sequential machines. The memory elements. Synthesis of synchronous sequential circuits. Minimization of finite state machines. Estimated time: 4 hours lectures + 8 hours exercises | T1 chapters 5 and 6, T3 |
| 3 | Design of a digital system. Design flow of a digital system. Datapath and control unit. Components of a digital system. Arithmetic circuits. Estimated time: 2 hours lectures + 2 hours exercises | T1 chapters 7 and 8, T2 chapter 3, T3 |
| 4 | The types of computers and their characteristics. The components of a computer. Computer Organization. Computer performance evaluation. Estimated time: 1 hour lectures + 2 hours exercises | T2 chapter 1, T3 |
| 5 | Instruction Set Architecture. Estimated time: 2 hours lectures | T2 chapter 2, T3 |
| 6 | Sequential organization of a processor. Datapath of a sequential processor. Control unit of a sequential processor. Estimated time: 2 hours lectures + 1 hour exercises | T2 chapter 4, T3 |
| 7 | Organization of pipelined processor. Pipeline Hazards. Estimated time: 4 hours lectures + 2 hours exercises | T2 chapter 4, T3 |
| 8 | Translation and starting a program: assembler, linker, and loader. An Instruction Set Simulator for RISC-V processor. Estimated time: 1 hour lectures + 1 hour exercises | T3 |
| 9 | Arithmetic/logical instructions. Memory access. Flow control instructions. Estimated time: 1 hour lectures + 4 hours exercises | T3 |
| 10 | System calls. Array. Strings. Procedure calls. Estimated time: 1 hour lectures + 4 hours exercises | T3 |
| 11 | Memory subsystem. Static and dynamic RAM memories. Estimated time: 2 hours lectures | T2 chapter 5, T3 |
| 12 | Cache memories. Block placement policies, block identification, block replacement and write policy. Cache Performance. Estimated time: 2 hours lectures + 1 hour exercises | T2 chapter 5, T3 |
| 13 | Techniques for improving cache performance. Estimated time: 2 hours lectures + 1 hour exercises | T2 chapter 5, T3 |
Learning Assessment
Learning Assessment Procedures
The exam consists of a single written and computer test. The exam includes:
- two exercises on circuit design (11 points);
- the development of an assembly program (7 points);
-a computer performance evaluation exercise and two question on computer architectures (14 points).
To pass the test it is necessary to obtain a minimum score of 18, with at least 6/11 points for the questions on circuit design, at least 4/7 points for the development of the assembly program and at least 8/14 points for the questions on architectures ( performance evaluation + computer architectures).
There are no ongoing tests.
Verification of learning can also be carried out by telematic means, if the conditions require it.