COMPUTER ARCHITECTURE A - L
Academic Year 2023/2024 - Teacher: Giuseppe ASCIAExpected Learning Outcomes
The course presents the fundamental concepts of computing systems.
In the first part the course introduces the techniques and methodologies for the design of digital systems.
In the second part, the course presents the components of a computer and their organization, some instruction set architectures of the processors, some techniques for an efficient implementation of the processors and the memory subsystem.
Furthermore, in order to better understand the functioning of the processor, the course introduces the student to the assembly programming of an educational processor.
Knowledge and understanding
The student will know:
- the basic techniques for the design of combinational and sequential digital circuits.
- technologies for the design of digital systems at different levels of abstraction.
- the elementary modules of a computer
- the main instruction set architectures.
- the basic architectures of RISC processors
- the assembly of an educational RISC processor
Applying knowledge and understanding
The student will be able to:
-design simple combinational and synchronous sequential circuits
-develop models of simple digital systems using the VHDL description language
- evaluate the performance of a computer and the impact of architectural choices on performance
-write programs in the assembly language of an educational processor
Making judgements
The student will be able to assess the impact of architectural choices on the performance of a computer.
Communication skills
The student will be able to clearly and rigorously present the acquired knowledge and how to apply it for the design and evaluation of simple computing systems.
Learning skills
The student will be able to independently learn:
- additional basic features of processor architectures
- the assembly of other processors
Course Structure
The course will be organized in lectures, exercises, practical experiences and presentation of use cases.
If the teaching is given in a mixed or remote mode, the necessary changes with respect to what was previously stated may be introduced, in order to respect the program planned and reported in the syllabus.
Required Prerequisites
Attendance of Lessons
Detailed Course Content
Part I Digital Design
1.1 Combinational circuits design
Switching Algebra. Minimum Boolean expressions. Minimization using Karnaugh maps and Quine-McCluckey method.
1.2 Synchronous sequential circuits Design
Introduction to sequential machines. The memory elements. Synthesis of synchronous sequential circuits. Minimization of finite state machines.
1.3 Design of a digital system
Design flow of a digital system. Datapath and control unit. Hardware description Languages. VHDL. Entity and architecture. Concurrent and sequential models. Process. Data types. Procedure and funtions. Simulations.
Part II Computer architecture
2.1 Computer abstractions and technology
The types of computers and their characteristics. The components of a computer. Computer Organization. Computer performance evaluation. Amdhal’s law.
2.2 The computer language: the Assembly
Instruction Set Architecture. Translation and starting a program: assembler, linker, and loader. MIPS64 Instruction Set Architecture. An educational Instruction Set Simulator for MIPS 64 processor. Assembly of MIPS64 processor. Arithmetic/logical instructions. Memory access. System calls. Array. String. Procedure calls
2.3 Computer Organization
Sequential organization of a processor. Datapath of a sequential processor. Control unit of a sequential processor.
Organization of pipelined processor. Pipeline Hazard. Performance evaluation of a pipelined processor. Techniques for detecting and resolving pipeline hazards. Code scheduling for hazard minimization.
2.4 The Memory subsystem.
Static and dynamic RAM memories. Asynchronous and synchronous memories. Memory organization.
Cache memories. Block placement policies, block identification, block replacement and write policy. Memory Performance. Techniques for improving cache performance.
Textbook Information
[T1] Fummi, Sami, Silvano, “Progettazione digitale”, 2/ed McGraw-Hill
[T2] Patterson, Hennessy, “Struttura e progetto dei calcolatori”, Zanichelli
[T3] Bucci, “Architettura e organizzazione dei calcolatori elettronici: fondamenti”, McGraw-Hill
[T4] On line Course material
Course Planning
Subjects | Text References | |
---|---|---|
1 | Combinational circuits design. Algebra. Minimum Boolean expressions. Minimization using Karnaugh maps and Quine-McCluckey method. | T1 chapters 3 and 4, T4 |
2 | Synchronous sequential circuits Design. Introduction to sequential machines. The memory elements. Synthesis of synchronous sequential circuits. Minimization of finite state machines. | T1 chapters 5 and 6, T4 |
3 | Design of a digital system. Design flow of a digital system. Datapath and control unit. Components of a digital system. Multiplexer, Decoder, Encoder, Comparator, Registers, Register file. | T1 chapters 7 and 8, T2 chapter 3, T4 |
4 | Adder. Multiplier and divisor. Design of an ALU | T1 chapters 7 and 8, T2 chapter 3, T4 |
5 | HDL languages. Development of a VHDL model. Simulation of a VHDL model. Testbench. | T1 appendix A, T4 |
6 | The types of computers and their characteristics. The components of a computer. Computer Organization. Computer performance evaluation. | T2 chapter 1, T3 chapter 5 T4 |
7 | Instruction Set Architecture. | T2 chapter 2, T3 chapter 5, T4 |
8 | Sequential organization of a processor. Datapath of a sequential processor. Control unit of a sequential processor. | T2 chapter 4, T3 chapter 7, T4 |
9 | Organization of pipelined processor. | T2 chapter 4, T4 |
10 | Translation and starting a program: assembler, linker, and loader. | T4 |
11 | An educational Instruction Set Simulator for MIPS64 processor | T4 |
12 | Arithmetic/logical instructions. Memory access. | T4 |
13 | System calls. Array. String. | T4 |
14 | Procedure calls. Stack pointer. | T4 |
15 | Static and dynamic RAM memories. Asynchronous and synchronous memories. Memory organization. | T2 chapter 5, T3 chapter 8, T4 |
16 | Cache memories. Block placement policies, block identification, block replacement and write policy. Cache Performance. | T2 chapter 5, T3 chapter 8, T4 |
17 | Techniques for improving cache performance. | T2 chapter 5, T3 chapter 8, T4 |
Learning Assessment
Learning Assessment Procedures
- two exercises on circuit design (8 points);
- the development of a VHDL model (5 points);
- the development of an assembly program (9 points);
-a computer performance evaluation exercise (3 points)
- a question on computer architectures (7 points).
To pass the test it is necessary to obtain a minimum score of 18, with at least 5/8 points for the questions on circuit design, at least 5/9 points for the development of the assembly program and at least 6/10 points for the questions on architectures ( performance evaluation + computer architectures).
There are no ongoing tests.
Verification of learning can also be carried out by telematic means, if the conditions require it.