ADVANCED COMPUTER ARCHITECTURES
Academic Year 2023/2024 - Teacher: Giuseppe ASCIAExpected Learning Outcomes
The course presents the concepts related to advanced architectures in modern information processing systems.
Starting from the basic architectures, the course addresses the problems and solutions relating to the execution of applications and presents the hardware and software methodologies for optimizing performance for the different forms of parallelism (instruction-level, data-level, thread-level ).
Knowledge and understanding
The student will know and understand:
- techniques for the optimal execution of applications in pipeline processors with floating point instructions
- issues and solutions related to exceptions in pipeline processors.
- branch prediction techniques
- the problems and solutions relating to the static and dynamic scheduling of instructions
- processor architectures that exploit forms of data level parallelism
- the different forms of thread-level parallelism and their implementations
- multiprocessor architectures
- problems and solutions for the coherence of cache memories in multiprocessor systems
Applied knowledge and understanding
The student will be able to evaluate the performance of modern microprocessor systems, to choose the best form of parallelism for a specific application and to propose possible optimizations.
Making judgements
The student will be able to evaluate the impact of architectural choices on the performance of computers.
Communication skills
The student will be able to clearly and rigorously present the acquired knowledge and how to apply it for the evaluation of the different architectural choices.
Learning skills
The student will be able to independently learn further advanced features of processor architectures
Course Structure
The course will be organized in lectures and exercises.
If the teaching is given in a mixed or remote mode, the necessary changes with respect to what was previously stated may be introduced, in order to respect the program planned and reported in the syllabus.
Required Prerequisites
Attendance of Lessons
Detailed Course Content
1) Basic Computer Architecture:
Pipelined processors (problems and solutions, implementation)
Branch prediction
Exceptions with pipelined execution
2) Instruction level parallelism
Static and dynamic scheduling.
Hardware-based Speculation, Multi-issue execution. Superscalar architectures: principles and problems.
VLIW (Very Long Instruction Word) architectures, examples of architectures families.
3) Data-level parallelism
Vector processors.
SIMD extensions.
4) Multiprocessors and thread level parallelism
Taxonomy, topologies, communication management, memory management.
Cache coherence protocols, examples of architectures
5) Application Specific Architectures
Textbook Information
[T1] Hennessy & Patterson: Computer architecture, a quantitative approach (Morgan Kaufmann eds.) 5 ed.
[T2] Patterson & Hennessy: “Struttura e progetto dei calcolatori”. Zanichelli 4. Ed
[T3] On line Course material
Course Planning
| Subjects | Text References | |
|---|---|---|
| 1 | Pipelined processors: problems and solutions. Pipelined execution of Floating Point instructions | T1 Appendix C, T2 Chapter 4 |
| 2 | Static and dynamic branch prediction techniques | T1 Chapter 3 |
| 3 | Exceptions with pipelined execution | T1 Appendix C, T2 Chapter 4 |
| 4 | Data and control dependence. Static and dynamic scheduling | T1 Chapter 3 |
| 5 | Dynamic scheduling with Scoreboard | T1 Chapter 3 |
| 6 | Dynamic scheduling with Tomasulo's Algorithm. | T1 Chapter 3 |
| 7 | Speculative execution and Reoder Buffer | T1 Chapter 3 |
| 8 | Superscalar architectures: multi-issue with static and dynamic scheduling | T1 Chapter 3 |
| 9 | VLIW (Very Long Instruction Word) architectures | T1 Appendix H |
| 10 | Processors architectures that exploit forms of data level parallelism | T1 Chapter 4 |
| 11 | Processor architectures that exploit forms of thread-level parallelism | T1 Chapter 5 |
| 12 | Multiprocessors | T1 Chapter 5 |
| 13 | Memory management in multiprocessors. The cache consistency protocols. | T1 Chapter 5 |
| 14 | Application Specific Architectures | T3 |
Learning Assessment
Learning Assessment Procedures
Students must take an oral exam.
The assessment of learning can also be conducted remotely if conditions require it.